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...the world's most energy friendly microcontrollers
5 Memory and Bus System
Quick Facts
What?
A low latency memory system including low
0 1 2 3
4
energy Flash and RAM with data retention
which makes the energy modes attractive.
Why?
RAM retention reduces the need for storing
data in Flash and enables frequent use of the
ultra low energy modes EM2 and EM3 with
ARM Cor t e x- M 3
DM A Con t r olle r
Fla sh
RAM
EBI
Pe r iph e r a ls
as little as 0.6 μA μA current consumption.
How?
Low energy and non-volatile Flash memory
stores program and application data
in all energy modes and can easily be
reprogrammed in system. Low leakage RAM
with data retention in EM0 to EM3 removes
the data restore time penalty, and the DMA
ensures fast autonomous transfers with
predictable response time.
5.1 Introduction
The EFM32G contains an AMBA AHB Bus system to allow bus masters to access the memory mapped
address space. A multilayer AHB bus matrix connects the 4 master bus interfaces to the AHB slaves
(Figure 5.1 (p. 14) ). The bus matrix allows several AHB slaves to be accessed simultaneously. An
AMBA APB interface is used for the peripherals, which are accessed through an AHB-to-APB bridge
connected to the AHB bus matrix. The 4 AHB bus masters are:
? Cortex-M3 ICode: Used for instruction fetches from Code memory (0x00000000 - 0x1FFFFFFF)
? Cortex-M3 DCode: Used for debug and data access to Code memory (0x00000000 - 0x1FFFFFFF)
? Cortex-M3 System: Used for instruction fetches, data and debug access to system space
(0x20000000 - 0xDFFFFFFFFF, 0xE0100000 - 0xFFFFFFFF)
? DMA: Can access entire memory space (0x00000000 - 0xFFFFFFFF)
2011-04-12 - d0001_Rev1.10
13
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